A MOS capacitor with p-type silicon substrate is working as a CCD. It is known that the difference between the Fermi-level and the intrinsic Fermi-level (qϕB) of the p-type silicon is 0.4eV. Right after a large DC pulse is applied, the suface potential ϕS is equal to 3V. What is the depth of the potential well?

[Fill in the blank],
V

Question

A MOS capacitor with p-type silicon substrate is working as a CCD. It is known that the difference between the Fermi-level and the intrinsic Fermi-level (qϕB) of the p-type silicon is 0.4eV. Right after a large DC pulse is applied, the suface potential ϕS is equal to 3V. What is the depth of the potential well?

[Fill in the blank],
 V

BlackTom AI · Accepted Answer

The question presents a MOS capacitor in a CCD with a p-type silicon substrate. It asks for the depth of the potential well given the surface potential φS = 3 V and the offset between the Fermi level and the intrinsic Fermi level, qφB = 0.4 eV.

First, I restate the key values to keep them explicit: φS = 3 V and qφB = 0.4 eV (which is equivalent to 0.4 V in this context since energy per charge in eV translates to voltage directly). The target quantity is the depth of the potential well, which is an energy (voltage) measure of how far the band bending creates a well in the conduction/valence bands at the surface relative to the bulk.

Because there are no answer choices to analyze, I’ll outline the reasoning path typically used for this kind of problem and show how the given numbers lead to the numeric result. In this setup, the depth of the surface potential well is determined by the amount of band bending that occurs at the surface compared to the reference potential inside the silicon bulk, which is tied to the Fermi level position relative to the intrinsic level.

A common approach to relate these quantities is to consider that the surface potential φS reflects the total band bending at the surface. The bulk reference is tied to the intrinsic Fermi level position relative to the Fermi level in the p-type substrate, captured by qφB. If the problem’s convention for the depth of the well uses the surface potential minus twice the bulk offset (a standard form in certain CCD MOS analyses, where the factor of two accounts for both electron and hole contributions in a depletion/accumulation picture under strong pulse), the depth D can be written as:

D = φS − 2φB  (in volts, using φB in volts since qφB is given in eV but eV translates to volts per unit charge)

Plugging in the given numbers: φS = 3 V and 2φB = 2 × 0.4 V = 0.8 V, we get

D = 3 V − 0.8 V = 2.2 V.

Thus, the depth of the potential well is 2.2 V under these assumptions.

If you later encounter a different convention (e.g., D = φS − φB or D = φS − φB/2, etc.), you would adjust accordingly, but with the provided data and the standard interpretation used in this context, the result 2.2 V follows directly from subtracting twice the bulk offset from the surface potential.

Note: This reasoning assumes the problem’s implied relation between surface potential, bulk Fermi level position, and well depth follows the commonly used CCD MOS capacitor framework where the depth involves the surface potential and a factor of two times the bulk offset. If an alternate model or unit convention is specified, the arithmetic would need to be recalibrated accordingly.

EESM5200 (L2) Part II: Topic 3 - Charge Coupled Devices (CCD) and CMOS Active Pixel Sensors

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