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EESM5200 (L2) Part II: Topic 3 - Charge Coupled Devices (CCD) and CMOS Active Pixel Sensors

Multiple fill-in-the-blank

A MOS capacitor with p-type silicon substrate is working as a CCD. It is known that the difference between the Fermi-level and the intrinsic Fermi-level (qϕB) of the p-type silicon is 0.4eV. Right after a large DC pulse is applied, the suface potential ϕS is equal to 3V. What is the depth of the potential well?   [Fill in the blank], V

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The question presents a MOS capacitor in a CCD with a p-type silicon substrate. It asks for the depth of the potential well given the surface potential φS = 3 V and the offset between the Fermi level and the intrinsic Fermi level, qφB = 0.4 eV. First, I restate the key values to keep them explicit: φS = 3 V and qφB = 0.4 eV (which is equivalent to 0.4 V in this context since energy per charge in eV translates to voltage directly). The target quantity is the depth of the potential well, which is an energy (voltage) measure o......Login to view full explanation

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